Signals in digital electronic systems must often be connected to many different circuit inputs, or sinks. In many cases, as with a clock signal, it is important that the difference in the arrival time of the signal at these various sinks, also known as the skew of the signal, be as small as possible, as this skew directly adds to the cycle time of the machine. In other cases, the objective is not to have the signal arrive at all sinks at the same time, but to maintain a certain fixed relationship or skew between the arrival times at different sinks. In both of these cases, it is important to minimize the amount of wiring required to achieve the desired skew, both to reduce the overall loading of the signal and to avoid unnecessary use of the limited "real estate" found on VLSI chips and other devices.
The following previous methods are described in various combinations in "Circuits, Interconnections, and Packaging for VLSI", Addison-Wesley, 1990, by H. B. Bakoglu; "High Performance Clock Distribution for CMOS ASICs", Proceedings of the 1989 CICC, p. 15.4.1 by Scot Boon, et al.; "SDC Cell--A novel CMOS/BiCMOS Design Methodology for Mainframe Arithmetic Module Generation", Proceedings of the 1989 CICC, p. 17.7.1 by Takehisa Hayashi, et al.; "A Hierarchical Floor-Planning, Placement, and Routing Tool for Sea-of-Gates Designs", Proceedings of the 1989 CICC, p. 3.3.1 by Charles Ng, et al.; and "Clock System Design", IEEE Design and Test of Computers, vol. 5, no. 5, October 1988, pp. 9-27 by Kenneth D. Wagner:
1. Use of special fixed wiring structures to distribute clock signals in order to minimize skew. This method is deficient in that it cannot adapt to nonuniform distributions of signal sinks.
2. Use of special buffer circuits capable of driving very large loads with small variations in delay to drive the signals whose skew is to be controlled and adjustment of the capacitive load on signals to equalize the delay through the buffers driving various signals whose skews are to be minimized. Both of these methods minimize the skew due to the delay through the buffers driving the signals, but are deficient in that they do not reduce the skew due to differences in the RC delays on the wiring feeding the different sinks of a signal.
3. Selection of special wire widths for clock distribution of signals whose skew is to be controlled in order to reduce the RC delay to the various sinks of the signal. This method is deficient in that these wide wires increase the capacitive loading on the circuits driving them, increasing the delay of those circuits, in that they require more area, reducing the wirability of the network, and in that the reduction in RC delay (and therefore skew) which can be achieved is limited by the product of the resistance per unit length of the wiring material and the capacitance per unit length of that material, which does not continue to decrease as the wire width increases, but reaches an asymptotic limit.
"Routing Techniques for Clock-Skew Minimization", 1990 Research Summary, U.C. Berkeley EECS/ERL, p. 17 by Michael Jackson and Arvind Scinivasan describes a method for building a signal distribution network as a tree, starting at the root of the tree (the source of the signal). This method is deficient in that a level of the tree is generated before the loading on other levels fed by them is known, so construction of said level cannot be optimized to account for the delay through said other levels.
"Clock Tree Synthesis for Large Gate Arrays", CADENCE Semicustom Design Guide, 1989, p. 32 by Al Chao describes another method for reducing skew in clock distribution network.